AROS / EFIKA
For posts on my effort to port AROS to the EFIKA powerpc board.
Thursday, July 31, 2008
BATS
So SmartFirmware starts up in virtual mode, and its memory is mapped back to itself, anyway, its handy to know.
User and Supervisor both have Read/Write access currently. Not sure why we have data mapped at 0x80000000.
IBAT1+DBAT0 corresponds to the MBAR. Maybe the data in DBAT3 is where the x86 video card is residing, its a common PCI memory space address…
The rest of the bats were full of junk and marked no-access more or less.
(BAT’s dump after the jump)
ibat0 00001FFF:00000012 covers 256mb from address 0x00000000 to 0x0FFFFFFF, mapped to 0x00000000 to 0x0FFFFFFF USM RW ibat1 F0001FFF:F0000012 covers 256mb from address 0xF0000000 to 0xFFFFFFFF, mapped to 0xF0000000 to 0xFFFFFFFF USM RW dbat0 F0001FFF:F000002A covers 256mb from address 0xF0000000 to 0xFFFFFFFF, mapped to 0xF0000000 to 0xFFFFFFFF USGI RW dbat1 80001FFF:8000002A covers 256mb from address 0x80000000 to 0x8FFFFFFF, mapped to 0x80000000 to 0x8FFFFFFF USGI RW dbat2 00001FFF:00000012 covers 256mb from address 0x00000000 to 0x0FFFFFFF, mapped to 0x00000000 to 0x0FFFFFFF USM RW dbat3 C0001FFF:C000002A covers 256mb from address 0xC0000000 to 0xCFFFFFFF, mapped to 0xC0000000 to 0xCFFFFFFF USGI RW
Filed Under : Computers • Development • AROS / EFIKA •
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Monday, July 28, 2008
Grins and Giggles
Just for grins and giggles, I’ve dumped the firmware tree, in order to help me find things… see below the jump
+--> #address-cells +--> #size-cells +--> device_type +--> model +--> revision +--> CODEGEN,vendor +--> CODEGEN,board +--> CODEGEN,description +--> openprom (+) | +--> CodeGen-copyright | +--> bplan-copyright | +--> SmartFirmware-version | +--> model | +--> relative-addressing | +--> built-on | +--> client-services (+) +--> aliases (+) | +--> ide | +--> hd | +--> eth | +--> screen +--> options (+) | +--> ac-back-behaviour | +--> security-password | +--> security-#badlogins | +--> security-mode | +--> fcode-debug? | +--> load-base | +--> virt-size | +--> virt-base | +--> real-size | +--> real-base | +--> real-mode? | +--> little-endian? | +--> inverse-video? | +--> oem-banner | +--> oem-banner? | +--> oem-logo? | +--> screen-#rows | +--> screen-#columns | +--> output-device | +--> input-device | +--> use-nvramrc? | +--> nvramrc | +--> client-ip | +--> server-ip | +--> secondary-diag? | +--> use-argv[0]? | +--> usb-enable? | +--> fb-mode | +--> diag-switch? | +--> diag-file | +--> diag-device | +--> boot-protocol | +--> boot-device | +--> boot-file | +--> boot-command | +--> auto-boot-timeout | +--> auto-boot? +--> packages (+) | +--> terminal-emulator (+) | | +--> iso6429-1983-colors | +--> deblocker (+) | +--> disk-label (+) | +--> obp-tftp (+) +--> chosen (+) | +--> stdin | +--> stdout | +--> bootpath | +--> bootargs | +--> memory | +--> mmu | +--> bootreply-packet +--> memory (+) | +--> device_type | +--> reg | +--> available +--> cpus (+) | +--> #size-cells | +--> #address-cells | +--> #cpus | +--> PowerPC,G2 (+) | | +--> device_type | | +--> reg | | +--> cpu-version | | +--> clock-frequency | | +--> bus-frequency | | +--> timebase-frequency | | +--> reservation-granule-size | | +--> state | | +--> tlb-size | | +--> tlb-sets | | +--> tlb-split | | +--> d-tlb-size | | +--> d-tlb-sets | | +--> i-tlb-size | | +--> i-tlb-sets | | +--> i-cache-line-size | | +--> i-cache-block-size | | +--> i-cache-size | | +--> i-cache-sets | | +--> d-cache-line-size | | +--> d-cache-block-size | | +--> d-cache-size | | +--> d-cache-sets | | +--> available | | +--> existing | | +--> translations +--> rtas (+) | +--> rtas-version | +--> rtas-size | +--> rtas-display-device | +--> rtas-event-scan-rate | +--> rtas-error-log-max | +--> restart-rtas | +--> nvram-fetch | +--> nvram-store | +--> get-time-of-day | +--> set-time-of-day | +--> set-time-for-power-on | +--> event-scan | +--> check-execption | +--> read-pci-config | +--> write-pci-config | +--> display-character | +--> set-indicator | +--> power-off | +--> suspend | +--> hibernate | +--> system-reboot | +--> aros,rtas-base | +--> aros,rtas-entry +--> failsafe (+) | +--> device_type +--> builtin (+) | +--> .description | +--> device_type | +--> model | +--> bus-frequency | +--> #address-cells | +--> #size-cells | +--> ranges | +--> reg | +--> compatible | +--> #interupt-cells | +--> interrupt-parent | +--> pic (+) | | +--> device_type | | +--> interrupt-controller | | +--> #interrupt-cells | | +--> .description | | +--> model | | +--> compatible | | +--> reg | +--> bestcomm (+) | | +--> device_type | | +--> .description | | +--> model | | +--> compatible | | +--> interrupts | | +--> reg | | +--> bestcomm_tasktable | +--> sram (+) | | +--> device_type | | +--> .description | | +--> model | | +--> compatible | | +--> reg | | +--> available | +--> ata (+) | | +--> device_type | | +--> .description | | +--> model | | +--> compatible | | +--> interrupts | | +--> reg | | +--> disk (+) | | | +--> device_type | | | +--> reg | | | +--> ata | | +--> bestcomm-task (+) | | | +--> device_type | | | +--> .description | | | +--> taskid | | | +--> revision | | | +--> interrupts | +--> usb (+) | | +--> .description | | +--> interrupts | | +--> reg | | +--> model | | +--> compatible | | +--> device_type | | +--> #address-cells | | +--> #size-cells | +--> ethernet (+) | | +--> device_type | | +--> .description | | +--> local-mac-address | | +--> mac-address | | +--> address-bits | | +--> max-frame-size | | +--> model | | +--> compatible | | +--> interrupts | | +--> reg | | +--> bestcomm-rxtask (+) | | | +--> device_type | | | +--> .description | | | +--> taskid | | | +--> revision | | | +--> interrupts | | +--> bestcomm-txtask (+) | | | +--> device_type | | | +--> .description | | | +--> taskid | | | +--> revision | | | +--> interrupts | +--> sound (+) | | +--> device_type | | +--> .description | | +--> model | | +--> compatible | | +--> interrupts | | +--> reg | | +--> bestcomm-rxtask (+) | | | +--> device_type | | | +--> .description | | | +--> taskid | | | +--> revision | | | +--> interrupts | | +--> bestcomm-txtask (+) | | | +--> device_type | | | +--> .description | | | +--> taskid | | | +--> revision | | | +--> interrupts | +--> serial (+) | | +--> device_type | | +--> .description | | +--> model | | +--> compatible | | +--> interrupts | | +--> reg | +--> pcidma (+) | | +--> device_type | | +--> .description | | +--> model | | +--> compatible | | +--> interrupts | | +--> reg | | +--> bestcomm-txtask (+) | | | +--> device_type | | | +--> .description | | | +--> taskid | | | +--> revision | | | +--> interrupts +--> pci (+) | +--> device_type | +--> #address-cells | +--> #size-cells | +--> clock-frequency | +--> ranges | +--> reg | +--> #interrupt-cells | +--> interrupt-map-mask | +--> bus-range | +--> interrupt-map | +--> display (+) | | +--> vendor-id | | +--> device-id | | +--> revision-id | | +--> class-code | | +--> subsystem-id | | +--> subsystem-vendor-id | | +--> .vendor-name | | +--> .class | | +--> .subclass | | +--> .progif | | +--> interrupts | | +--> devsel-speed | | +--> 66mhz-capable | | +--> fast-back-to-back | | +--> min-grant | | +--> max-latency | | +--> cache-line-size | | +--> reg | | +--> device_type | | +--> rom | | +--> assigned-addresses | +--> display (+) | | +--> vendor-id | | +--> device-id | | +--> revision-id | | +--> class-code | | +--> subsystem-id | | +--> subsystem-vendor-id | | +--> .vendor-name | | +--> .class | | +--> .subclass | | +--> devsel-speed | | +--> 66mhz-capable | | +--> fast-back-to-back | | +--> min-grant | | +--> max-latency | | +--> cache-line-size | | +--> reg | | +--> assigned-addresses
Filed Under : Computers • Development • AROS / EFIKA •
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Not a huge achievement but its a step
Right now I’m trying to fully parse the device tree so I can leave OF and jump into AROS.
The next step is to write the MPC5200 SOC drivers AROS needs (scheduler, mmu, timer, etc)
(The relevant bit is at the bottom of the boot message)
EFIKA 5K2 Boot Strap [RELEASE BUILD] (c) 2002-2007 bplan GmbH (BUILD 20070122 84240)
Running on CPU PVR: 0x80822014
Running on system SVR: 0x80110022
BIOS Code position: 0xFFF040D0
Setup System Config… Done.
Setup Memory Config… Done.
Setup PCI… Done.
Setup ATA… Done.
Setup USB… Done.
Setup ETH… Done.
Setup AC97… Done.
Testing 08000000 Bytes, Pass: 00000000 Failed: 00000000
RAM TEST (fill random)... Done.
cpu0: PowerPC,G2 CPUClock 396 Mhz BUSClock 132 Mhz (Version 0x8082,0x2014)
channel 0 unit 0 : ata | ST920217A | 3.01
ATA device not present or not responding
EMULATION INT HANDLER ENTERED WITH:
INT NO: 15
EAX=0003 EBX=1111 ECX=2222 EDX=3333 ESP=0000 EBP=5555 ESI=6666 EDI=7777
AX=4E08 BX=C405 CX=0003 DX=102A SP=6C1C BP=5555 SI=5C6B DI=7777
DS=C000 ES=BAD0 SS=C000 CS=F000 IP=FE15 NV UP -- PL ZR NA PE NC
CS:IP = F4 FS=BAD4 GS=BAD5C4CA C000 0244 3000 0000 01B4 ABD5 0200
UNHANDLED INT 10 FUNCTION 0007 WITHIN EMULATION
VM using 1657003 x86 cycles for GFX init
Welcome to SmartFirmware(tm) for bplan EFIKA5K2
Version 1.3 (20070122084838)
SmartFirmware(tm) Copyright 1996-2001 by CodeGen, Inc.
All Rights Reserved.
Pegasos BIOS Extensions Copyright 2001-2007 by bplan GmbH.
All Rights Reserved.
ok boot eth:0192.168.0.102 loader
** EFIKA Init **
BOARD : EFIKA5K2, revision 2B3
OpenFirmware : 1.3, 20070122
CPU : Version 0x8082 (Revision 0x2014), v2.2, 396 MHz (Bus 132 MHz)
MBAR is at 0xF0000000
scanning memory:
block 0 - 131072kb at 0x00000000
block 1 - 16kb at 0xF0008000
Memory : 128MB
RTAS : base 0x7ffb000, entry 0x7ffb000, size=0x43bc
** OUT **
Filed Under : Computers • Development • AROS / EFIKA •
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Saturday, July 26, 2008
PowerPC Assembly
So I’m slowly getting my head around PPC assembly. Its not too dissimilar to x86 (in the backwardness), but ugh, loading things in high/low combinations. erugh.
Anyway, IEEE 1275 Open Firmware specs dictate what the register state be on load, so I’m hoping thats what the efika will present me.
The sooner I can get out of the assembler bootstrap and back into the C bootstrap the better
... Will see if the MBAR is at 0x80000000 or not like reset say it supposed to be…
Filed Under : Computers • Development • AROS / EFIKA •
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Wednesday, July 23, 2008
bootup.. not.. down..
Well we have a compiled bootloader but it doesnt yet properly talk OF/PROM. I think the biggest reason is I did not specify a start routine and just linked it to a binary.
Its a start, I hope soon to at least have some kind of brnigup on the bootloader.
Filed Under : Computers • Development • AROS / EFIKA •
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Sunday, July 20, 2008
Lets start work
So, now I have a half decent tool chain, its time to start working on
make kernel-bootloader-efika-ppc
The first build issue is its looking for a proto/kernel.h
I know WHERE its looking for it… Only that its generated, in the sense that the AROS build system copies it from who knows where or pre-generates it from some other file..
Finding where it comes from is the damn hard part.
Filed Under : Computers • Development • AROS / EFIKA •
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